View ADA4806-1ARJZ-R7_8374287.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

0.2 v/c off set drift, 105 mhz, lo w power, multimode, rail - to - rail amplifier data sheet ada4806 - 1 features ultralow supply current full power mode: 500 a sleep mode: 7 4 a shutdown mode: 2.9 a dynamic power scaling t urn - on time from shutdown mode : 1.5 s turn - on time from sleep mode : 0.45 s high speed performance with dc precision input offset voltage: 125 v maximum input offset voltage drift: 1.5 v/c maximum ? 3 db bandwidth: 105 mhz slew rate : 160 v/ s low noise and distortion 5.9 nv/hz input voltage noise with 8 hz 1/f corner ?102 dbc/?126 dbc hd2/hd3 at 100 khz wide supply range: 2.7 v to 10 v small package: 8 - lead sot - 23 applications portable and battery - powered instruments and systems high channel density data acquisition systems precision analog - to - digital converter (adc) drivers voltage reference buffer s portable point of sales terminals active rfid readers general description the ada4806 - 1 is a high speed, voltage feedback, rail - to - rail output, single operational amplifier with three power modes : full power mode , sleep mode, and shutdown mode . in full p ower mode, this amplifie r provides a wide bandwidth of 105 mhz at a gain of +1, a fast slew rate 160 v/s , and excellent dc precision with a low input offset voltage of 125 v (maximum) and an input offset voltage drift of 1.5 v/c (maximum) , while con - suming only 500 a of quiescent current. despite being a low power amplifier , the ada4806 - 1 provides excellent overall performance , making it ideal for low power, high resolution data conversion systems. for data conversion applications where minimizing power dissipation is paramount, the ada4806 - 1 offers a method to reduce power by dynamically scaling the quiescent power of the adc driver with the sampling rate of the system by switching the amplifier to a lower power mode between samples. typical applications circuit 13391-001 5v 2.5v ref c2 10f c1 2.7nf in+ ref gnd vdd vdd in? c3 0.1f c4 100nf ada4806-1 5v 0v to v ref ada4806-1 ad7980 r3 20? figure 1 . driving the ad7980 with the ada4806 - 1 s leep mode reduces the amplifier quiescent current to 74 a and provides a fast turn - on time of only 0.45 s , enabling the use of dynamic power scaling for sample rates approaching 2 msps. for additional power savings at lower samples rates, the shutdown mo de further reduces the quiescent current to only 2.9 a . the ada4806 - 1 operates over a wide range of supply volt ages and is fully specified at supplies of 3 v, 5 v and 5 v. this amplifier is available in a compact , 8 - lead sot - 23 package and is rated to operate over the industrial temperature range of ?40c to +125c. 13391-6 1 1 power consumption (mw) adc sample rate (ksps) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 10 100 1000 sleep mode shutdown mode figure 2 . quiescent power dissipation vs. adc sample rate , using dynamic power scaling for the two low power modes table 1 . complementary adcs to the ada4806 -1 product adc power (mw) throughput (msps) resolution (bits) snr (db ) ad7980 4.0 1 16 9 0.5 1 ad7982 7.0 1 18 98 ad7984 10.5 1.33 18 98.5 1 this snr value is for the a grade version of the ad7980 . rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chang e without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 020 62- 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www. analog.com
ada4806 - 1 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical applications circuit ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v supply ................................................................................... 3 5 v supply ...................................................................................... 4 3 v supply ...................................................................................... 6 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 maximum power dissipation ..................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 test circuits ..................................................................................... 17 theory of oper ation ...................................................................... 18 amplifier description ................................................................ 18 input protection ......................................................................... 18 shutdown/sleep mode operation ............................................ 18 noise considerations ................................................................. 19 applications information .............................................................. 20 slew enhancement ..................................................................... 20 effect of feedback resistor on frequency response ............ 20 compensating peaking in large signal frequency response ... 20 driving low power, high resolution successive approximation register (sar) adcs ..................................... 20 dynamic power scaling ............................................................. 21 single - ended to differential conversion ................................... 23 layout considerations ............................................................... 23 outline dimensions ....................................................................... 24 ordering g uide .......................................................................... 24 revision history 9 /15 revision 0 : initial version rev. 0 | page 2 of 24
data sheet ada4806 - 1 specifications 5 v supply v s = 5 v at t a = 25c; r f = 0 ? for g = +1; otherwise, r f = 1 k?; r l = 2 k? to ground; unless otherwise noted. table 2. parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth g = +1, v out = 0.02 v p -p 120 mhz g = +1, v out = 2 v p -p 40 mhz bandwidth for 0.1 db flatness g = +1, v out = 0.02 v p - p 18 mhz slew rate g = +1, v out = 2 v step 190 v/s g = +2, v out = 4 v step 250 v/s settling time to 0.1% g = +1, v out = 2 v step 35 n s g = +2, v out = 4 v step 78 n s noise/distortion performance harmonic distortion, hd2/hd3 1 f c = 20 khz, v out = 2 v p -p ?114/? 140 dbc f c = 100 khz, v out = 2 v p -p ?102/?128 dbc f c = 20 khz, v out = 4 v p - p, g = +1 ?109/? 143 dbc f c = 100 khz, v out = 4 v p - p, g = +1 ?93/? 130 dbc f c = 20 khz, v out = 4 v p - p, g = +2 ?113/?142 dbc f c = 100 khz, v out = 4 v p - p, g = +2 ?96/?130 dbc input voltage noise f = 100 khz 5.2 nv/hz input voltage noise 1/f corner frequency 8 hz 0.1 hz to 10 hz voltage noise 44 nv rms input current noise f = 100 khz 0.7 pa/hz dc performance input offset voltage full power mode 13 125 v low power mode , sleep = ?v s 800 v input offset voltage drift 2 t min to t max , 4 0.2 1.5 v/c input bias current (i b ) full power mode 550 800 na low power mode , sleep = ?v s 3 na input offset current 2.1 25 na open - loop gain v out = ?4.0 v to +4.0 v 107 111 db input characteristics input resistance common mode 50 m? differential mode 260 k? input capacitance 1 pf input common - mode voltage range ?5.1 +4 v common - mode rejection ratio (cmrr) v in, cm = ?4.0 v to +4.0 v 103 130 db shutdown pin shutdown voltage low powered down ?0.9 v shutdown current low powered down ?1.0 + 0.2 a high enabled 0.02 1.0 a turn - off time 50% o f shutdown to <10% of enabled quiescent current 1.25 2.75 s turn - on time 50% of shutdown t o >99 % of final v out 1 3 s rev. 0 | page 3 of 24
ada4806 - 1 data sheet parameter test conditions/comments min typ max unit sleep pin sleep voltage low powered down < ?1.3 v high enabled > ?0.9 v sleep current low low power mode, sleep = ?v s ?1.0 + 0.2 a high enabled 0.02 1.0 a turn - off time (full power mode to sleep mode) 50% of sleep to 3 0% of enable d quiescent current 180 240 n s turn - on time ( sleep mode to full power mode) 50% of sleep to >99 % of final v out 450 600 n s output characteristics output overdrive recovery time (rising/falling edge) v in = +6 v to ?6 v, g = +2 95/100 n s output voltage swing r l = 2 k? ?4.98 +4.98 v short - circuit current sourcing/sinking; f ull power mode 85/73 ma sourcing/sinking; l ow power mode , sleep = ?v s 1.4/1.8 ma linear output current <1 % total harmonic distortion ( thd ) at 100 kh z, v out = 2 v p -p 58 ma off isolation v in = 0.5 v p - p, f = 1 mhz , shutdown = ?v s 41 db capacitive load drive 30% overshoot 15 pf power supply operating range 2.7 10 v quiescent current per amplifier full power mode 570 625 a low power mode , sleep = ?v s 85 a shutdown = ?v s 7.4 12 a power supply rejection ratio (psrr) positive +v s = + 3 v to + 5 v, ?v s = ?5 v 100 119 db negative +v s = + 5 v, ?v s = ?3 v to ?5 v 100 122 db 1 f c is the fundamental frequency. 2 guaranteed, but not tested. 5 v supply v s = 5 v at t a = 25c; r f = 0 ? for g = +1; otherwise, r f = 1 k?; r l = 2 k? to mid supply; unless otherwise noted. table 3. parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth g = +1, v out = 0.02 v p -p 105 mhz g = +1, v out = 2 v p -p 35 mhz bandwidth for 0.1 db flatness g = +1, v out = 0.02 v p -p 20 mhz slew rate g = +1, v out = 2 v step 160 v/s g = +2, v out = 4 v step 220 v/s settling time to 0.1% g = +1, v out = 2 v step 35 ns g = +2, v out = 4 v step 82 ns rev. 0 | page 4 of 24
data sheet ada4806 - 1 parameter test conditions/comments min typ max unit noise/distortion performance harmonic distortion, hd2/hd3 1 f c = 20 khz, v out = 2 v p -p ?114/? 135 dbc f c = 100 khz, v out = 2 v p -p ?102/?126 dbc f c = 20 khz, g = +2, v out = 4 v p -p ?107/?1 43 dbc f c = 100 khz, g = +2, v out = 4 v p - p ?90/?1 30 dbc input voltage noise f = 100 khz 5.9 nv/hz input voltage noise 1/f corner 8 hz 0.1 hz to 10 hz voltage noise 54 nv rms input current noise f = 100 khz 0.6 pa/hz dc performance input offset voltage full power mode 10 125 v low power mode , sleep = ?v s 500 v input offset voltage drift 2 t min to t max , 4 0.2 1.5 v/c input bias current full power mode 470 720 na low power mode , sleep = ?v s 3 na input offset current 0.4 na open - loop gain v out = 1.25 v to 3.75 v 105 109 db input characteristics input resistance common mode 50 m? differential mode 260 k? input capacitance 1 pf input common - mode voltage range ?0.1 +4 v common - mode rejection ratio v in, cm = 1.25 v to 3.75 v 103 133 db shutdown pin shutdown voltage low powered down <1.5 v high enabled >1.9 v shutdown current low powered down ?1.0 + 0.1 a high enabled 0.01 1.0 a turn - off time 50 % of shutdown to <10% of e nabled quiescent current 0.9 1.25 s turn - on time 50% of shutdown to >99 % of final v out 1.5 4 s sleep pin sleep voltage low powered down <1.5 v high enabled >1.9 v sleep current low low power mode , sleep = ?v s ?1.0 + 0.1 a high enabled 0.01 1.0 a turn - off time (full power mode to sleep mode) 50% of sleep to 3 0% of enable d quiescent current 150 185 n s turn - on time ( sleep mode to full power mode) 50% of sleep to >99 % of final v out 450 600 n s rev. 0 | page 5 of 24
ada4806 - 1 data sheet parameter test conditions/comments min typ max unit output characteristics overdrive recovery time (rising/falling edge) v in = ?1 v to +6 v, g = +2 130/145 ns output voltage swing r l = 2 k? 0.02 4.98 v short - circuit current sourcing/sinking; f ull power mode 73/63 ma sourcing/sinking; l ow power mode , sleep = ?v s 1.0/1.3 m a linear output current <1% thd at 100 khz, v out = 2 v p -p 47 ma off isolation v in = 0.5 v p - p, f = 1 mhz, shutdown = ?v s 41 db capacitive load drive 30% overshoot 15 pf power supply operating range 2.7 10 v quiescent current per amplifier full power mode 500 520 a low power mode , sleep = ?v s 74 a shutdown = ?v s 2.9 4 a power supply rejection ratio positive +v s = 1.5 v to 3.5 v, ?v s = ?2.5 v 100 120 db negative +v s = 2.5 v, ?v s = ?1.5 v to ?3.5 v 100 126 db 1 f c is the fundamental frequency. 2 guaranteed, but not tested. 3 v supply v s = 3 v at t a = 25c; r f = 0 ? for g = +1; otherwise, r f = 1 k?; r l = 2 k? to midsupply; unle ss otherwise noted. table 4. parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth g = +1, v out = 0.02 v p -p 95 mhz g = +1, v out = 1 v p - p, +v s = 2 v, ?v s = ?1 v 30 mhz bandwidth for 0.1 db flatness g = +1, v out = 0.02 v p -p 35 mhz slew rate g = +1, v out = 1 v step, +v s = 2 v, ?v s = ?1 v 85 v/s settling time to 0.1% g = +1, v out = 1 v step 41 ns noise/distortion performance harmonic distortion, hd2/hd3 1 f c = 20 khz, v out = 1 v p - p, +v s = 2 v, ?v s = ?1 v ?123/?143 dbc f c = 100 khz, v out = 1 v p - p, +v s = 2 v, ?v s = ?1 v ?107/?13 3 dbc input voltage noise f = 100 khz 6.3 nv/hz input voltage noise 1/f corner 8 hz 0.1 hz to 10 hz voltage noise 55 nv rms input current noise f = 100 khz 0.8 pa/hz dc performance input offset voltage full power mode 7 125 v low power mode , sleep = ?v s 300 v input offset voltage drift 2 t min to t max , 4 0.2 1.5 v/c input bias current full power mode 440 690 na low power mode , sleep = ?v s 3 na input offset current 0.5 na open - loop gain v out = 1.1 v to 1.9 v 100 107 db rev. 0 | page 6 of 24
data sheet ada4806 - 1 parameter test conditions/comments min typ max unit input characteristics input resistance common mode 50 m? differential mode 260 k? input capacitance 1 pf input common - mode voltage range ?0.1 +2 v common - mode rejection ratio v in, cm = 0.5 v to 2 v 89 117 db shutdown pin shutdown voltage low powered down <0.7 v high enabled >1.1 v shutdown current low powered down ?1.0 + 0.1 a high enabled 0.01 1.0 a turn - off time 50% of shutdown to < 10% of enabled quiescent current 0.9 1.25 s turn - on time 50% of shutdown to >99 % of final v out 2.5 8 s sleep pin sleep voltage low powered down <0.7 v high enabled >1.1 v sleep current low low power mode, sleep = ?v s ?1.0 + 0.1 a high enabled 0.01 1.0 a turn - off time (full power mode to sleep mode) 50% of sleep to 3 0% of enable d quiescent current 155 210 n s turn - on time ( sleep mode to full power mode) 50% of sleep to >99 % of final v out 450 600 n s output characteristics output overdrive recovery time (rising/falling edge) v in = ?1 v to +4 v, g = +2 135/175 ns output voltage swing r l = 2 k? 0.02 2.98 v short - circuit current sourcing/sinking; f ull power mode 65/47 ma sourcing/sinking; l ow power mode , sleep = ?v s 1.0/1.3 ma linear output current <1% thd at 100 khz, v out = 1 v p -p 40 ma off isolation v in = 0.5 v p - p, f = 1 mh z, shutdown = ?v s 41 db capacitive load drive 30% overshoot 15 pf power supply operating range 2.7 10 v quiescent current per amplifier full power mode 470 495 a low power mode , sleep = ?v s 70 a shutdown = ?v s 1.3 3 a power supply rejection ratio positive +v s = 1.5 v to 3.5 v, ?v s = ?1.5 v 96 119 db negative +v s = 1.5 v, ?v s = ?1.5 v to ?3.5 v 96 125 db 1 f c is the fundamental frequency. 2 guaranteed, but not tested. rev. 0 | page 7 of 24
ada4806 - 1 data sheet absolute maximum rat ings table 5. parameter rating supply voltage 11 v power dissipation see figure 3 common - mode input voltage ?v s ? 0.7 v to +v s + 0.7 v differential input voltage 1 v storage temperature range ?65c to +125c operating temperature range ?40c to +125c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other cond itions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst case cond itions, that is, ja is specified f or a device soldered in a circuit board for surface - mount packages . table 6 lists the ja for the ada4806 - 1 . table 6 . thermal resistance package type ja unit 8- lead sot -23 209.1 c/w maximum power dissip ation the maximum safe power dissipation for the ada4806 - 1 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c, which is the glass transition temperature, the properties of the plastic change. even temporaril y exceeding this temperature limit may change the stresses that the package exerts on the die, p ermanently shifting the parametric performance of the ada4806 - 1 . exceeding a ju nction temperature of 175 c for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the p ower dissipated in the die due to the ada4806 - 1 output load drive. the quiescent power dissipation is the voltage between the supply pins ( v s ) multiplied by the quiescent current (i s ). p d = quiescent power + ( total drive power ? load power ) ( ) l out l out s s s d r v r v v i v p 2 2 ? ? ? ? ? ? ? ? ? + = ( ) ( ) l s s s d r v i v p 2 4 / + = esd caution rev. 0 | page 8 of 24
data sheet ada4806 - 1 pin configuration and function descrip tions v out 1 nc 2 ?v s 3 +v s 8 shutdown notes 1. nc = no connection. do not connect t o this pin. 7 6 +in 4 ?in 5 13391-002 slee p ada4806-1 figure 4 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 v out output. 2 nc no connection. do not connect to this pin. 3 ?v s negative supply. 4 +in noninverting input. 5 ?in inverting input. 6 sleep low power mode . 7 shutdown power - down mode . 8 +v s positive supply. rev. 0 | page 9 of 24
ada4806 - 1 data sheet typical performance characteristics r l = 2 k?, unless otherwise noted. when g = +1, r f = 0 ? . ?12 ?9 ?6 ?3 0 3 0.1 1 10 100 1000 normalized closed-loo p gain (db) frequenc y (mhz) g = +1 g = +10 v s = 2.5v v out = 20mv p-p r l = 2k r f = 1k g = +5 g = +2 13391-206 figure 5 . small signal frequency response for various gains ?12 ?9 ?6 ?3 0 3 0.1 1 10 100 1000 closed-loo p gain (db) frequenc y (mhz) v s = 2.5v g = +1 v out = 20mv p-p r l = 2k ?40c +25c +125c 13391-208 figure 6 . small signal frequency response for various temperatures ?12 ?9 ?6 ?3 0 3 0.1 1 10 100 1000 closed-loo p gain (db) frequenc y (mhz) g = +1 v out = 20mv p-p r l = 2k v s = 1.5v v s = 2.5v v s = 5v 13391-207 figure 7 . small signal frequency response for various supply voltages ?12 ?9 ?6 ?3 0 3 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) v s = 2.5v v out = 2v p-p r f = 1k r l = 2k g = +2 g = +5 g = +10 g = +1 13391-015 figure 8 . large signal frequency response for various gains ?9 ?6 ?3 0 3 0.1 1 10 100 closed-loo p gain (db) frequenc y (mhz) v s = 2.5v g = +1 v out = 2v p-p r l = 2k +25c +125c ?40c 13391-016 figure 9 . large signal frequency response for various temperatures frequenc y (mhz) ?6 ?3 0 3 0.1 1 10 100 1000 closed-loo p gain (db) v s = 2.5v g = +1 r l = 2k v out = 20mv p-p v out = 0.5v p-p v out = 2v p-p v out = 100mv p-p 13391-2 1 1 figure 10 . frequency response for various output voltages rev. 0 | page 10 of 24
data sheet ada4806 - 1 ?12 ?9 ?6 ?3 0 3 6 9 12 1 10 100 closed-loo p gain (db) frequenc y (mhz) v s = 2.5v g = +1 r l = 2k v out = 20mv p-p 13391-309 c l = 15pf c l = 10pf c l = 5pf c l = 0pf c l = 15pf r s = 226 figure 11 . small signal frequency response for various capacitive loads (see figure 47 ) ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 1 10 100 1000 dis t ortion (dbc) frequenc y (khz) hd2, g = +1 v s = 5 v , v out = 4v p-p hd2, g = +2 hd3, g = +1 hd3, g = +2 13391-514 figure 12 . distortion vs. frequency for various gains ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 t o t a l harmonic dis t ortion (db) output vo lt age (v peak) input common-mode vo lt age upper limit (+v s ? 1v) v s = 2.5v v in, cm = 0v g = +1 r l = 2k v in = 1mhz v in = 100khz v in = 10khz 13391-316 figure 13 . total harmonic distortion v s. output voltage for various frequencies ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 1 10 100 closed-loo p gain (db) frequenc y (mhz) v s = 2.5v g = +1 r l = 2k v out = 20mv p-p 13391- 1 10 figure 14 . small signal 0.1 db bandwidth ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 1 10 100 1000 dis t ortion (dbc) frequenc y (khz) hd3 v s = +2v/?1v hd3 v s = 5v hd3 v s = 2.5v hd2 v s = +2v/?1v hd2 v s = 5v hd2 v s = 2.5v v s = 5 v , v out = 2v p-p v s = 2.5 v , v out = 2v p-p v s = +2v/?1 v , v out = 1v p-p 13391-517 figure 15 . distortion vs. frequency for various supplies, g = +1 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 1 10 100 1000 dis t ortion (dbc) frequenc y (khz) hd2 v s = 2.5v hd2 v s = +2v/?1v hd3 v s = +2v/?1v hd3 v s = 2.5v hd2 v s = 5v hd3 v s = 5v v s = 5 v , v out = 4v p-p v s = 2.5 v , v out = 4v p-p v s = +2v/?1 v , v out = 1v p-p 13391-518 figure 16 . disto rtion vs. frequency, g = +2 rev. 0 | page 11 of 24
ada4806 - 1 data sheet 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 1k 10k 100k 1m 10m 100m vo lt age noise (nv/hz) frequenc y (hz) v s = 2.5v g = +1 13391-219 figure 17 . voltage noise vs. frequency ?300 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 0 1 2 3 4 5 6 7 8 9 10 amplitude (nv) time (seconds) v s = 2.5v a verage noise = 54nv rms 13391-318 figure 18 . 0.1 hz to 10 hz voltage noise ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 10 100 1k 10k 100k 1m 10m 100m frequenc y (hz) ?psrr +psrr cmrr cmrr, psrr (db) v s = 2.5v v s , v cm = 100mv p-p 13391-232 figure 19 . cmrr, psrr vs. frequency 0 2 4 6 8 10 12 1 10 100 1k 100k 10k current noise (pa/hz) frequenc y (hz) 10m 1m v s = 2.5v g = +1 13391-018 figure 20 . current noise vs. frequency (see figure 48 ) 13391-601 isolation (db) frequency (mhz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0.01 0.1 1 10 100 v s = 2.5v g = +1 r l = 2k v in = 0.5 vp-p shutdown = ?v s sleep = ?v s figure 21 . forward isolation vs. frequency v s = +5v g = +1 v out = 2v ste p r l = 2k settling (%) ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 20 40 60 80 100 time (ns) 120 140 160 180 13391-030 figure 22 . settling time to 0.1% rev. 0 | page 12 of 24
data sheet ada4806 - 1 13391-613 number of units input offset vo lt age (v) 0 ?120 ?90 ?60 ?30 0 30 60 90 120 500 1000 1500 2000 2500 3000 3500 4000 4500 v s = 2.5v = 9.8v = 19.5v figure 23 . input offset voltage distribution ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ? 3.0 ? 2.5 ? 2.0 ? 1.5 ?1 .0 ? 0.5 0 0.5 1.0 1.5 2.0 input offset vo lt age (v) input common-mode vo lt age (v) v s = 2.5v 10 units 13391-327 figure 24 . input offset voltage vs. input common - mode voltage ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 input bias current ( na) temper a ture (c) v s = 2.5v v s = 1.5v v s = 5v 390 410 430 450 470 490 510 530 550 570 590 610 630 650 13391-257 figure 25 . input bias current vs. t emperature for various supplies (see figure 49 ) 0 5 10 15 20 25 30 35 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 units (%) input offset vo lt age drift (v/c) v s = 2.5v t = ?40c t o +125c = ?0.19v/c = 0.28v/c 13391-323 figure 26 . input offset voltage drift distribution ?150 ?100 ?50 0 50 100 150 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 input offset vo lt age (v) temper a ture (c) v s = 2.5v 30 units 13391-013 figure 27 . input offset voltage vs. temperature ? 6 ? 4 ? 2 0 2 4 6 ?800 ?750 ?700 ?650 ?600 ?550 ?500 ?450 ?400 ? 0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 input offset current (na) input bias current (na) input common-mode vo lt age (v) input offset current i b+ i b? 13391-135 figure 28 . input bias current and input offset current vs. input common - mode voltage rev. 0 | page 13 of 24
ada4806 - 1 data sheet ?15 ?10 ?5 0 5 10 15 0 50 100 150 200 250 300 output vo lt age (mv) time (ns) g = +1 v out = 20mv p-p v s = 5v v s = 1.5v v s = 2.5v 13391-024 figure 29 . small signal transient respo nse for various supplies 0 10 0 20 0 30 0 40 0 50 0 t i me ( n s ) 60 0 70 0 80 0 90 0 100 0 ? 3 ? 4 ? 2 ? 1 0 1 2 3 4 i n p u t and o u t p u t vo l t a g e (v) v s = 2 . 5 v g = +1 v i n v o u t 13391-128 figure 30 . input overdrive recovery time 13391-602 output voltage (v) time (s) ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 ?0.5 0.5 1.5 1.0 2.0 v s = 2.5v g = +1 r l = 2k +125c +25c ?40c figure 31 . turn - on response time f rom shutdown f or v arious temperatures (see figure 50 ) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 50 100 150 200 250 350 300 output vo lt age (v) time (ns) v s = 1.5 v , v in, cm = ?0.5 v , v out = 1v p-p v s = 2.5 v , v in, cm = 0 v , v out = 2v p-p v s = 5 v , v in, cm = 0 v , v out = 2v p-p g = +1 13391-025 figure 32 . large signal transient respo nse for various supplies ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 input and output vo lt age (v) v s = 2. 5v g = +2 2v in v out 0 100 200 300 400 500 time (ns) 600 700 800 900 1000 13391-129 figure 33 . output overdrive recovery time 13391-605 output voltage (v) time (s) ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?0.25 0 0.25 0.50 0.75 +125c +25c ?40c v s = 2.5v g = +1 r l = 2k rev. 0 | page 14 of 24
data sheet ada4806 - 1 0 100 200 300 400 500 600 700 800 0 1 ?1 2 3 4 5 6 supp l y current (a) time (s) +125c +25c ? 40c v s = 2.5v g = +1 r l = 2k 13391-258 figure 35 . turn - off response time to shutdown for various temperatures (see figure 51 ) 13391-603 output voltage (v) time (s) ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?1 0 1 2 3 g = +1 r l = 2k v s = +2/?1v v s = 2.5v v s = 5v figure 36 . turn - on response time from shutdown for various supplies 0 100 200 300 400 500 600 800 700 0 1 ?1 2 3 4 5 6 supp l y current (a) time (s) v s = 1.5v v s = 5v v s = 2.5v g = +1 r l = 2k 13391-242 figure 37 . turn - off response time to shutdown for various supplies 13391-607 supply current (a) time (s) 0 100 200 300 400 500 600 700 800 ?1 0 1 2 3 4 5 6 v s = 2.5v g = +1 r l = 2k +125c +25c ?40c figure 38 . turn - off response time t o sleep for various temperatures (see figure 51 ) 13391-608 output voltage (v) time (s) ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.5 ?0.25 0.25 0.75 g = +1 r l = 2k v s = 5v v s = +2v/?1v v s = 2.5v figure 39 . turn - on response time from sleep for various supplies 13391-609 supply current (a) time (s) 0 100 200 300 400 500 600 700 800 ?1 0 1 2 3 4 5 6 g = +1 r l = 2k v s = 5v v s = 2.5v v s = 1.5v figure 40 . turn - off response time to sleep for various supplies rev. 0 | page 15 of 24
ada4806 - 1 data sheet 300 350 400 450 500 550 600 650 700 750 800 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 quiescent supp l y current ( a) temper a ture (c) v s = 2.5v v s = 1.5v v s = 5v 13391-256 figure 41 . quiescent supply current vs. temperature 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 shutdown and slee p threshold (v) supp l y vo lt age from ground (v) +125c +25c ?40c 13391-236 figure 42 . shutdown and sleep t hreshold vs. supply voltage from ground for various temperatures 21.5 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 0 200 400 600 800 1000 1200 1400 temper a ture (c) change in input offset vo lt age (v) time (hours) oi l b a th temper a ture v s = 2.5v 6 units, soldered t o pcb 13391-542 figure 43 . long - term v os drift 13391-606 quiescent supply current (a) temperature (c) 40 50 70 90 110 60 80 100 120 130 140 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 v s = 2.5v v s = 1.5v v s = 5.0v figure 44 . sleep mode quiescent supply current vs. temperature 13391-604 output current (ma) temperature (c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 v s = 2.5v v s = 1.5v v s = 5.0v figure 45 . sleep mode output current vs. temperature ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m open-loo p phase (degrees) open-loo p gain (db) frequenc y (hz) gain phase 13391-026 figure 46 . open - loop gain and phase margin rev. 0 | page 16 of 24
data sheet ada4806 - 1 test circuits 50 ? r s +2.5v ?2.5v v out 2k c l v in 20mv p-p 13391-401 figure 47 . output capacitive load behavior test circuit (see figure 11 ) 75k +2.5v ?2.5v v out 13391-402 figure 48 . current noise test circuit (see figure 20 ) i b + i b ? 13391-403 figure 49 . input bias current temperature test circuit (see figure 25) ?2.5v 0.5v 5v + ? ?2.5v shutdown or slee p +2.5v v out 2k 13391-404 figure 50 . turn - o n response test circuit (see figure 31 and figure 34) ?2.5v i s ?2.5v +2.5v v out 2k 5v + ? 13391-405 shutdown or slee p figure 51 . turn - o ff response test circuit (see figure 35 and figure 38) rev. 0 | page 17 of 24
ada4806 - 1 data sheet theory of operation amplifier descriptio n the ada4806 - 1 has a bandwidth of 105 mhz a nd a slew rate of 160 v/s. it has an input referred voltage noise of only 5.9 nv/hz. the ada4806 - 1 operate s over a supply voltage range of 2.7 v t o 10 v and consume s only 500 a of supply current at v s = 5 v. the low end of the supply range allows ? 10% variation of a 3 v supply. the amp lifier is unity - gain stable, and the input structure results in an extremely low input 1/f noise. the ada4806 - 1 use s a slew enhancement architecture, a s shown in figure 52 . the slew enhancement circuit detects the absolute difference between the two inputs. it then modulates the tail current, i tail , of the input stage to boost the sl ew rate. the architecture allows a higher slew rate and fast settling time with low quiescent curre nt while maintaining low noise. +in v in+ v in? +v s input st age t o detect absolute v alue slew enhancement circuit i tail ?in 13391-255 figure 52 . slew enhancement circuit input protection the ada4806 - 1 is fully protected from esd events, withstanding human body model esd events of 3.5 kv and ch arged device model events of 1.25 kv with no measured performance degradation. the precision input is protected with an esd network between the power supplies and diode clamps across the input device pair, as shown in figure 53 . +in esd esd ?v s +v s bias to the rest of the amplifier ?in esd esd 13391-005 figure 53 . input stage and protection diodes for differential voltages above approximately 1.2 v at room temperature, and 0.8 v at 125c, the diode clamps begin to conduct. if large differential voltages must be sustained across the input terminals, the current through the input clamps must be limite d to less than 10 ma. series input resistors that are sized appropriately for the expected differential overvoltage provide the needed protection. the esd clamps begin to conduct for input voltages that are more than 0.7 v above the positive supply and inp ut voltages more than 0.7 v below the negative supply. if an overvoltage condition is expected, the input current must be limited to less than 10 ma. shutdown / sleep mode operation figure 54 shows the ada4806 - 1 shutdown circuitry. to maintain very low supply current in shutdown mode, no internal pull - up resistor is supplied; therefore, the shutdown pin must be driven high or low externally and must not be left floating. pulling the shutdown pin to 1 v below midsupply turns the device off, reducing the supply current to 2.9 a for a 5 v supply . when the amplifier is powered down, its output enters a high impedance state. the output impedance decreases as frequency increases. in shutdown mode, a forward isolation of ? 62 db can be achieved at 100 khz (see figure 21 ). a second circuit similar to figure 54 i s used for sleep mode operation. pulling the sleep pin low places the amplifier in a low powe r state, drawing only 74 a from a 5 v supply. leaving the amplifier biased on at a very low level greatly reduces the turn - on time from sleep to full power mode, thus enabling dynamic power scaling of the ada4806 - 1 at higher sample rates. the ada4806 - 1 is not characterized for operation in sleep mode. +v s ?v s shutdown esd esd 2.2r 1.8r 1.1v to enable amplifier 13391-006 figure 54 . shutdown / sleep equivalent circuit the shutdown pin and the sleep pin are protected by esd clamps, as shown in figure 54 . voltages beyond the power supplies cause these diodes to conduct. to protect the shutdown and sleep pin s , ensure that the volt age to these pin s does not exceed 0.7 v above the positive supply or 0.7 v below the negative supply. if an overvoltage condition is expected, the input current must be limited to less than 10 ma with a series resistor . rev. 0 | page 18 of 24
data sheet ada4806 - 1 table 8 summarizes the threshold voltages for the shutdown and sleep pins for various supplies. table 9 shows the truth table for the shutdown and sleep pins. table 8 . thresho ld voltages for enabled mode and shutdown/ sleep modes mode +3 v +5 v 5 v +7 v/?2 v enabled > + 1.1 v > + 1.9 v >?0.9 v > + 1.6 v shutdown/ sleep mode < + 0.7 v < + 1.5 v ada4806 - 1 data sheet applications information slew enhancement the ada4806 - 1 has an internal slew enhancement circuit that increases the slew rate as the feedback error voltage increases. this circuit allows the amplifier to settle a large step response faster, as shown in figure 57 . this is useful in adc applications where multiple input signals are multiplexed. the impact of the slew enhancement can also be seen in the large signal frequency response, where larger input signals cause a slight increase in pea king, as shown in figure 58. time (ns) output vo lt age (v) 50 40 30 20 10 0 100 90 80 70 60 v out = 500m v p -p ?0.5 ?1.0 ?1.5 0.5 0 1.0 1.5 v out = 2v p-p v out = 1v p-p v s = 2.5v g = +1 r l = 2k 13391-254 figure 57 . step response with selected output steps ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 normalized gain (db) frequenc y (hz) v s = 2.5v g = +1 r l = 2k? v in = 400mv p-p v in = 100mv p-p v in = 200mv p-p 100k 1m 10m 100m v in = 632mv p-p v in = 2v p-p 13391-105 figure 58 . peaking in frequency responses as signal level changes, g = +1 effect of feedback r esistor on frequency response the amplifier input capacitance and feedback resistor form a pole that, for larger value feedback resistors, can reduce phase margin and cont ribute to peaking in the frequency response. figure 59 shows the peaking for selected feedback resistors ( r f ) when the amplifier is configured in a gain of +2. figure 59 also shows how peaking can be mitigated with the addition of a small value capacitor plac ed across the feedback resistor of the amplifier. ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 normalized gain (db) frequenc y (hz) 100k 1m 10m 100m r f = 1k? r f = 2.6k? r f = 2.6k?, c f = 1pf r f = 4.99k? r f = 4.99k?, c f = 1pf v s = 2.5v g = +2 r l = 2 k? v in = 20mv p-p 13391-106 figure 59 . peaking in frequency response at selected r f values compensating peaking in large signal frequency response at high frequency , the slew enhancement circuit can contribu te to peaking in the large signal frequency response. figure 59 shows the effect of a feedback capacitor on the small signal response , whereas figure 60 shows that the same technique is effective for reducing peaking in the large signal response. ?15 ?12 ?9 ?6 ?3 0 3 6 normalized gain (db) frequenc y (hz) v s = 2.5v g = +2 r l = 2 k? v in = 632mv p-p r f = 2.6k?, c f = 0pf r f = 1k?, c f = 0pf r f = 2.6k?, c f = 2.7pf r f = 1 k?, c f = 2 pf 100k 1m 10m 100m 13391-107 figure 60 . peaking mitigation in large signal frequency response driving low power, h igh resolution successive approxima tion regis ter ( sar ) adc s the ada4806 - 1 is ideal for driving low power, high resolution sar adc s . the 5.9 nv/hz input voltage noise and rail - to - rail output stage of the ada4806 - 1 help minimize distortion at large output levels. with its low power of 500 a, the amplifier consumes power that is compatible with low power sar adc s , which are usually in the micro watt (w) to low milliwatt (mw) range. furthermore, the ada4806 - 1 support s a single - supply configuration; the input common - mode range extends to 0.1 v below the negative supply, and 1 v belo w the positive supply. rev. 0 | page 20 of 24
data sheet ada4806 - 1 figure 61 shows a typical 16 - bit , single - supply application. the ada4806 - 1 drive s the ad7980 , a 16 - bit, 1 msps , sar adc in a low power configuration. the ad7980 operates on a 2.5 v supply and supports an input from 0 v to v ref . in this case, the adr435 provides a 5 v reference. the ada4806 - 1 is used both as a driver for the ad7980 and as a reference buffer for the adr435 . the low - pass filter formed by r3 and c1 reduces the noise to the input of the adc (see figure 61 ). in lower frequency applications, the designer can reduce the corner frequency of the fil ter to remove additional noise. ad7980 c2 10f in+ in? gnd vdd ref c3 0.1f c4 100nf vdd c1 2.7nf r3 20? +7.5v +7.5v ada4806-1 ada4806-1 adr435 5v ref 0v t o v ref 13391-310 figure 61 . driving the ad7980 with the ada4806 - 1 in this configuration, the ada4806 - 1 consume 7.2 mw of quiescent power. the measured signal - to - noise ratio ( snr ) , thd , and signal - to - noise - and - distortion ratio (sinad) of the whole system for a 10 khz signal are 89.4 db, 104 dbc , and 89. 3 db, respectively. this translates to an effective number of bits (enob) of 14.5 at 10 khz, which is compatible with the ad7980 performance. table 10 shows the performance of this setup at selected input frequencies. dynamic power scalin g one of the merits of a sar adc , like the ad7980 , is that its power scales with the sampling rate. this power scaling makes sar adcs very power efficient, especially when running at a low sampling frequency . however, the adc driver used with the sar adc traditionally consume s constant power regardless of the sampling frequency. figure 62 illustrates a method by which the quiescent power of the adc driver can be dynamically scaled with th e sampling rate of the system. by providing properly timed signals to the convert input (cnv) pin of the adc and the shutdown and sleep pin s of the ada4806 - 1 , both devices can be run at optimum efficiency . +5v 2.7nf 20 timing gener a t or v in ad7980 ada4806-1 ref vdd gnd +6v +2.5v 0.1 f cnv 13391-330 figure 62 . ada4806 - 1 / ad7980 power management circuitry figure 63 illustrates the relative signal timing for power scaling the ada4806 - 1 and the ad7980 . to prevent any degradation in the performance of the adc, the ada4806 - 1 must have a fully settled output into the adc before the activation of the cnv pin . the amplifier on - time (t amp, on ) is the time the amplifier is enabled prior to the rising edge of the cnv signal; this time depend s on whether the shutdown pin or sleep pin is being driven. in the example shown in figure 64, t amp, on is 3 s for the shutdown pin a nd 0.5 s for the sleep pin. after a conversion , the shutdown pin and /or the sleep pin of the ada4806 - 1 are pulled low when the adc input is inactive in between samples. while in shutdown mode, the ada4806 - 1 output impedance is high . table 10 . system perform ance at selected input frequencies for driving the ad7980 single - ended adc driver reference buffer results input frequency (khz) supply (v) gain supply (v) gain snr (db) thd (dbc) sinad (db) enob 1 7.5 1 7.5 1 89.8 103 89.6 14.6 10 7.5 1 7.5 1 89.4 104 89.3 14.5 20 7.5 1 7.5 1 89.9 103 89.7 14.6 50 7.5 1 7.5 1 88.5 99 88.1 14.3 100 7.5 1 7.5 1 86.3 93.7 85.6 13.9 rev. 0 | page 21 of 24
ada4806 - 1 data sheet sampling period, t s acquisition acquisition acquisition powered on powered on powered on i q, on t am p , off t am p , off t am p , off t am p , on t am p , on t am p , on adc cnv ada4806-1 shutdown/ slee p shutdown/slee p shutdown/slee p shutdown/slee p conversion conversion conversion ada4806-1 quiescent current 13391-329 figure 63 . timing waveforms figure 64 shows the quiescent power of the ada4806 - 1 , operating from a single +6 v supply, with out power scaling and while power scalin g via the shutdown pin and the sleep pin . without power scaling, the ada4806 - 1 consumes constant power regardless of the sampling frequency , as shown in equation 1 . p q = i q v s (1) with power scaling, the quiescent power becomes proportional to the ratio between the amplifier on time, t amp, on , and the sampling time, t s : ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 13391-612 quiescent power consumption (mw) adc sample rate (ksps) 0.01 0.01 0.1 1.0 10 0.1 1 10 100 1000 continuously on sleep mode shutdown mode ad7980 adc figure 64 . quiescent power consumption of the ada4806 - 1 vs. adc sample rate , using dynamic power scaling rev. 0 | page 22 of 24
data sheet ada4806 - 1 single - ended to differentia l conversion most high resolution adc s have differential inputs to reduce common - mode noise and harmonic distortion. therefore, it is necessary to use an amplifier to convert a single - ended signal into a differential signal to drive the adc s . there are two common ways the user can convert a si ngle - ended signal into a differential signal: either use a differential amplifier, or configure two amplifiers as shown in figure 65 . the use of a dif ferential amplifier yields better performance, whereas the 2 - op - amp solution results in lower system cost. the ada4806 - 1 solve s this dilemma of choosing between the two methods by combining the advantages of both. its low harmonic distortion, low offset voltage, and low bias current mean that it can produce a differential output that is well matched with the performance of the high resolution adc s . figur e 65 shows how the ada4806 - 1 convert s a single - ended signal into a differential output. the first amplifier is configure d in a gain of +1 with its output then inverted to produce the complementary signal. the differential output then drives the ad7982 , an 18 - bit, 1 msps sar adc. to further reduce noise, the user can reduce the values of r1 and r2. however, note that this increases the power consumption. the low - pass filter of the adc driver limits the noise to the adc. the measured snr, thd, and sinad of the whole system for a 10 khz signal are 93 db, 113 db c, and 93 db, respectively. this translates to an enob of 15. 1 at 10 khz, which is compatible with the performance of the ad7982 . table 11 shows the performance of this setup at selected input frequencies . table 11 . system performance at selected input frequenc ies for driving the ad7982 differentially results input frequency (khz) snr (db) thd (dbc) sinad (db) enob 1 93 104 93 15.1 10 93 113 93 15.1 20 93 110 93 15.1 50 92 102 91 14.8 100 89 96 88 14.3 layout consideration s to ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. ground plane it is important to avoid ground in the areas under and around the in put and output of the ada4806 - 1 . stray capacitance between the ground plane and the input and output pads of a device is detrimental to high speed amplifier performance. stray capacitance at the inverting input, together with the amplifier input capacitance, lowers the phase margin and can cause instability. stray capacitance at the output creates a pole in the feedback loop, which can reduce phase margin and cause the circuit to become unsta ble. power supply bypassing power supply bypassing is a critical aspect in the performance of the ada4806 - 1 . a parallel connection of capacitors from each power supply pin to ground works best. smaller value ceramic capacitors offer better high frequency response, whereas larger value ceramic capacitors offer better low frequency performance. paralleling differ ent values and sizes of capacitors helps to ensure that the power supply pins are provided with a low ac impedance across a wide band of frequencies. this is important for minimizing the coupling of noise into the amplifier especially when the amplifier ps rr begins to roll off because the bypass capacitors can help lessen the degradation in psrr performance. place the smallest value capacitor on the same side of the board as the amplifier and as close as possible to the amplifier power supply pins. connect the ground end of the capacitor directly to the ground plane. it is recommended that a 0.1 f ceramic capacitor with a 0508 case size be used. the 0508 case size offers low series inductance and excellent high frequency performance. place a 10 f electroly tic capacitor in parallel with the 0.1 f capacitor. depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. each circuit is different and must be analyzed individually for optimal performance. ada4806-1 ada4806-1 v in +7.5v +7.5v +2.5v +2.5v vdd r1 1k? r2 1k? c2 2.7nf c1 0.1f c3 2.7nf c4 0.1f r3 22? r4 22? ad7982 in+ in? ref +5v vdd 13391-053 figure 65 . driving the ad7982 with the ada4806 - 1 rev. 0 | page 23 of 24
ada4806 - 1 data sheet outline dimensions c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 7 8 - b a 8 4 0 s e a t i n g p l a n e 1 . 9 5 b s c 0 . 6 5 b s c 0 . 6 0 b s c 7 6 1 2 3 4 5 3 . 0 0 2 . 9 0 2 . 8 0 3 . 0 0 2 . 8 0 2 . 6 0 1 . 7 0 1 . 6 0 1 . 5 0 1 . 3 0 1 . 1 5 0 . 9 0 0 . 1 5 m a x 0 . 0 5 m i n 1 . 4 5 m a x 0 . 9 5 m i n 0 . 2 2 m a x 0 . 0 8 m i n 0 . 3 8 m a x 0 . 2 2 m i n 0 . 6 0 0 . 4 5 0 . 3 0 p i n 1 i n d i c a t o r 8 1 2 - 1 6 - 2 0 0 8 - a figure 66 . 8 - lead small outline transistor package [sot - 23] (rj - 8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ada4806 - 1 arjz -r2 ?40c to +125c 8- lead small outline transistor package [sot -23] rj -8 ada4806 - 1 arjz -r7 ?40c to +125c 8- lead small outline transistor package [sot -23] rj -8 ada4806 - 1rj - ebz evaluation board for 8 - lead sot -23 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13391 - 0 - 9/15(0 ) rev. 0 | page 24 of 24

▲Up To Search▲

Price & Availability of ADA4806-1ARJZ-R7

	To Download ADA4806-1ARJZ-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .